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| Presentation | 2007-08-23 16:00 [Panel Discussion] Dynamic Voltage & Frequency Scaling ; A Key Technology for Deep Sub-100nm SoCs ! Tadayoshi Enomoto (Chuo Univ.), Naohiko Irie (Hitachi), Hiroshi Okano (Fujitsu), Shiro Sakiyama (Matsushita), Masakatsu Nakai (Sony), Koji Nii (Renesas Technology), Masahiro Nomura (NEC), Hiroyuki Mizuno (Hitachi)  SDM2007-154 ICD2007-82 Link to ES Tech. Rep. Archives: SDM2007-154 ICD2007-82 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | (Not available yet) | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | / / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 195, ICD2007-82, pp. 75-78, Aug. 2007. | |
| Paper # | ICD2007-82 | |
| Date of Issue | 2007-08-16 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2007-154 ICD2007-82 Link to ES Tech. Rep. Archives: SDM2007-154 ICD2007-82 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2007-08-23 - 2007-08-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitami Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamic Voltage & Frequency Scaling ; A Key Technology for Deep Sub-100nm SoCs ! |
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| 1st Author's Name | Tadayoshi Enomoto |
| 1st Author's Affiliation | Chuo University (Chuo Univ.) |
| 2nd Author's Name | Naohiko Irie |
| 2nd Author's Affiliation | Hitachi (Hitachi) |
| 3rd Author's Name | Hiroshi Okano |
| 3rd Author's Affiliation | Fujitsu (Fujitsu) |
| 4th Author's Name | Shiro Sakiyama |
| 4th Author's Affiliation | Matsushita (Matsushita) |
| 5th Author's Name | Masakatsu Nakai |
| 5th Author's Affiliation | Sony (Sony) |
| 6th Author's Name | Koji Nii |
| 6th Author's Affiliation | Renesas Technology (Renesas Technology) |
| 7th Author's Name | Masahiro Nomura |
| 7th Author's Affiliation | NEC (NEC) |
| 8th Author's Name | Hiroyuki Mizuno |
| 8th Author's Affiliation | Hitachi (Hitachi) |
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| Speaker | Author-1 |
| Date Time | 2007-08-23 16:00:00 |
| Presentation Time | 120 minutes |
| Registration for | ICD |
| Paper # | SDM2007-154, ICD2007-82 |
| Volume (vol) | vol.107 |
| Number (no) | no.194(SDM), no.195(ICD) |
| Page | pp.75-78 |
| #Pages | 4 |
| Date of Issue | 2007-08-16 (SDM, ICD) |
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