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Paper Abstract and Keywords
Presentation 2007-08-23 11:10
Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application
Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho (Matsushita) SDM2007-146 ICD2007-74
Abstract (in Japanese) (See Japanese page) 
(in English) Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of power supply, consumes much power; hence, we have devised a new architecture called a multiphase-output level shift system (M-LS) which has only three transistors in each LS and cuts off short current perfectly. Moreover, we have connected between the adjacent phases of M-LS with a resistor to improve phase accuracy. The two key techniques mentioned above make power consumption 1/15 of the conventional LS. The PLL consumes about 1mA at 123MHz and accomplishes 63-phase accuracy of 0.5LSB.
Keyword (in Japanese) (See Japanese page) 
(in English) Multiphase Clock / PLL / Level Shift System / Low Power / High Phase Accuracy / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 195, ICD2007-74, pp. 29-34, Aug. 2007.
Paper # ICD2007-74 
Date of Issue 2007-08-16 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-146 ICD2007-74

Conference Information
Committee ICD SDM  
Conference Date 2007-08-23 - 2007-08-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitami Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) 
Paper Information
Registration To ICD 
Conference Code 2007-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application 
Sub Title (in English)  
Keyword(1) Multiphase Clock  
Keyword(2) PLL  
Keyword(3) Level Shift System  
Keyword(4) Low Power  
Keyword(5) High Phase Accuracy  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Akinori Matsumoto  
1st Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita)
2nd Author's Name Shiro Sakiyama  
2nd Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita)
3rd Author's Name Yusuke Tokunaga  
3rd Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita)
4th Author's Name Takashi Morie  
4th Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita)
5th Author's Name Shiro Dosho  
5th Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita)
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Speaker Author-1 
Date Time 2007-08-23 11:10:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2007-146, ICD2007-74 
Volume (vol) vol.107 
Number (no) no.194(SDM), no.195(ICD) 
Page pp.29-34 
#Pages 6 
Date of Issue 2007-08-16 (SDM, ICD) 

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