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| Presentation | 2007-08-24 16:05 A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial)  SDM2007-168 ICD2007-96 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slower as fabrication is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write access at the same row by using DBSA with the 8T-SRBL memory cell. A rise of the storage node causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BL×512WL 64Kb 2port SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 2port SRAM / Single Bit Line / 8T Memory Cell / Hierarchical Bit Line / Simultaneous Read/Write Access / Misread / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 195, ICD2007-96, pp. 145-148, Aug. 2007. | |
| Paper # | ICD2007-96 | |
| Date of Issue | 2007-08-16 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2007-168 ICD2007-96 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2007-08-23 - 2007-08-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitami Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues |
| Sub Title (in English) | |
| Keyword(1) | 2port SRAM |
| Keyword(2) | Single Bit Line |
| Keyword(3) | 8T Memory Cell |
| Keyword(4) | Hierarchical Bit Line |
| Keyword(5) | Simultaneous Read/Write Access |
| Keyword(6) | Misread |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Satoshi Ishikura |
| 1st Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| 2nd Author's Name | M. Kurumada |
| 2nd Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| 3rd Author's Name | Toshio Terano |
| 3rd Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| 4th Author's Name | Yoshinobu Yamagami |
| 4th Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| 5th Author's Name | Naoki Kotani |
| 5th Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| 6th Author's Name | Katsuji Satomi |
| 6th Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| 7th Author's Name | Koji Nii |
| 7th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 8th Author's Name | Makoto Yabuuchi |
| 8th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 9th Author's Name | Yasumasa Tsukamoto |
| 9th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 10th Author's Name | Shigeki Ohbayashi |
| 10th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 11th Author's Name | Toshiyuki Oashi |
| 11th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 12th Author's Name | Hiroshi Makino |
| 12th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 13th Author's Name | Hirofumi Shinohara |
| 13th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 14th Author's Name | Hironori Akamatsu |
| 14th Author's Affiliation | Matsushita Electric Industrial Co., Ltd. (Matushita Electric Industrial) |
| Speaker | Author-1 |
| Date Time | 2007-08-24 16:05:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SDM2007-168, ICD2007-96 |
| Volume (vol) | vol.107 |
| Number (no) | no.194(SDM), no.195(ICD) |
| Page | pp.145-148 |
| #Pages | 4 |
| Date of Issue | 2007-08-16 (SDM, ICD) |
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