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Paper Abstract and Keywords
Presentation 2007-09-07 14:20
CAIRN3: An FPGA Implementation of the Sieving Step with the Lattice Sieving
Takeshi Shimoyama, Tetsuya Izu, Jun Kogure (FUJITSU) ISEC2007-84
Abstract (in Japanese) (See Japanese page) 
(in English) The hardness of the integer factorization problem assures the security of some public-key cryptosystems including RSA, and the number field sieve method (NFS), the most efficient algorithm for factoring large integers currently,is a threat for such cryptosystems. Recently, Izu et al.\ developed a dedicated sieving device CAIRN 2 with Xilinx's FPGA which is designed to handle up to 768-bit integers. However, since CAIRN 2 uses the line sieving, it is not optimized from the viewpoint of the efficiency. In this paper, we report some results of an FPGA-based sieving hardware CAIRN 3 with the lattice sieving. In the experimental sieving for a 768-bit integer (RSA768),CAIRN 3 is about 38 times faster than CAIRN 2. It is estimated that the full sieving for RSA768 requires about 270 years with single CAIRN 3.
Keyword (in Japanese) (See Japanese page) 
(in English) Integer factorization / the number field sieve method (NFS) / the sieving step / implementation / FPGA / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 209, ISEC2007-84, pp. 77-83, Sept. 2007.
Paper # ISEC2007-84 
Date of Issue 2007-08-31 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ISEC  
Conference Date 2007-09-07 - 2007-09-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2007-09-ISEC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) CAIRN3: An FPGA Implementation of the Sieving Step with the Lattice Sieving 
Sub Title (in English)  
Keyword(1) Integer factorization  
Keyword(2) the number field sieve method (NFS)  
Keyword(3) the sieving step  
Keyword(4) implementation  
Keyword(5) FPGA  
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Keyword(7)  
Keyword(8)  
1st Author's Name Takeshi Shimoyama  
1st Author's Affiliation FUJITSU Limited (FUJITSU)
2nd Author's Name Tetsuya Izu  
2nd Author's Affiliation FUJITSU Limited (FUJITSU)
3rd Author's Name Jun Kogure  
3rd Author's Affiliation FUJITSU Limited (FUJITSU)
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Speaker Author-3 
Date Time 2007-09-07 14:20:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # ISEC2007-84 
Volume (vol) vol.107 
Number (no) no.209 
Page pp.77-83 
#Pages 7 
Date of Issue 2007-08-31 (ISEC) 

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