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| Presentation | 2007-10-25 10:10 VLSI Architecture Based on Data Compression and Its Application Hisashi Yoshida (Tohoku Univ.), Yasuhiro Kobayashi (Oyama National College of Technology), Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)  SIP2007-111 ICD2007-100 IE2007-70 Link to ES Tech. Rep. Archives: ICD2007-100 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | To design low-power and high-speed image processors, the reduction of the number of interconnection units plays an important role. This paper presents a data-compression-based VLSI architecture that reduces the number of interconnection units between processing elements and memory modules without performance degradation. For example of a stereo matching VLSI, the number of interconnection units is reduced to 25%. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Image compression / Differential encoding / Memory architecture / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 287, ICD2007-100, pp. 11-14, Oct. 2007. | |
| Paper # | ICD2007-100 | |
| Date of Issue | 2007-10-18 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SIP2007-111 ICD2007-100 IE2007-70 Link to ES Tech. Rep. Archives: ICD2007-100 |
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| Conference Information | |
| Committee | SIP ICD IE IPSJ-SLDM |
| Conference Date | 2007-10-25 - 2007-10-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Aidu-Higasiyama-Onsen Kuturogijuku |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-10-SIP-ICD-IE-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | VLSI Architecture Based on Data Compression and Its Application |
| Sub Title (in English) | |
| Keyword(1) | Image compression |
| Keyword(2) | Differential encoding |
| Keyword(3) | Memory architecture |
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| 1st Author's Name | Hisashi Yoshida |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Yasuhiro Kobayashi |
| 2nd Author's Affiliation | Oyama National College of Technology (Oyama National College of Technology) |
| 3rd Author's Name | Masanori Hariyama |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 4th Author's Name | Michitaka Kameyama |
| 4th Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-10-25 10:10:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | SIP2007-111, ICD2007-100, IE2007-70 |
| Volume (vol) | vol.107 |
| Number (no) | no.285(SIP), no.287(ICD), no.289(IE) |
| Page | pp.11-14 |
| #Pages | 4 |
| Date of Issue | 2007-10-18 (SIP, ICD, IE) |
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