Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2007-10-30 15:50
Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs
Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.) VLD2007-59 SDM2007-203
Abstract (in Japanese) (See Japanese page) 
(in English) We have developed a system consisting of a full-3D process simulator for stress calculation and k·pband calculation that takes into account the subband structure. Our simulations are in good agreement with the experimental data of strained Si-pMOSFETs of 65nm technology devices. This system is a powerful tool to optimize device structures with all stress components.
Keyword (in Japanese) (See Japanese page) 
(in English) strain / stress / PMOS / kp method / 65nm / simulation / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 297, SDM2007-203, pp. 43-46, Oct. 2007.
Paper # SDM2007-203 
Date of Issue 2007-10-23 (VLD, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-59 SDM2007-203

Conference Information
Committee SDM VLD  
Conference Date 2007-10-30 - 2007-10-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process, Device, Circuit Simulation, etc. 
Paper Information
Registration To SDM 
Conference Code 2007-10-SDM-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs 
Sub Title (in English)  
Keyword(1) strain  
Keyword(2) stress  
Keyword(3) PMOS  
Keyword(4) kp method  
Keyword(5) 65nm  
Keyword(6) simulation  
Keyword(7)  
Keyword(8)  
1st Author's Name Eiji Tsukuda  
1st Author's Affiliation Renesas Technology (Renesas)
2nd Author's Name Yoshinari Kamakura  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Hiroyuki Takashino  
3rd Author's Affiliation Renesas Technology (Renesas)
4th Author's Name Takeshi Okagaki  
4th Author's Affiliation Renesas Technology (Renesas)
5th Author's Name Tetsuya Uchida  
5th Author's Affiliation Renesas Technology (Renesas)
6th Author's Name Takashi Hayashi  
6th Author's Affiliation Renesas Technology (Renesas)
7th Author's Name Motoaki Tanizawa  
7th Author's Affiliation Renesas Technology (Renesas)
8th Author's Name Katsumi Eikyu  
8th Author's Affiliation Renesas Technology (Renesas)
9th Author's Name Shoji Wakahara  
9th Author's Affiliation Renesas Technology (Renesas)
10th Author's Name Kiyoshi Ishikawa  
10th Author's Affiliation Renesas Technology (Renesas)
11th Author's Name Osamu Tsuchiya  
11th Author's Affiliation Renesas Technology (Renesas)
12th Author's Name Yasuo Inoue  
12th Author's Affiliation Renesas Technology (Renesas)
13th Author's Name Kenji Taniguchi  
13th Author's Affiliation Osaka University (Osaka Univ.)
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2007-10-30 15:50:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # VLD2007-59, SDM2007-203 
Volume (vol) vol.107 
Number (no) no.295(VLD), no.297(SDM) 
Page pp.43-46 
#Pages 4 
Date of Issue 2007-10-23 (VLD, SDM) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan