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Paper Abstract and Keywords
Presentation 2007-11-22 09:00
Designing Soft Error Tolerant LUTs of SRAM-based FPGAs
Kohei Satoyama, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST) RECONF2007-43
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, soft error becomes a serious problem as the process shrinks. Especially, SRAMs seriously suffer from soft error, and thus various techniques have been proposed to deal with it. In this paper, we proposes a technique, which we call "XOR swap," to achieve the majority voting of the TMR (Triple Module Redundancy) by using only the double memory cost. This technique can correct arbitrary random 1-bit error, and we confirmed that the error tolerance by the proposed technique is almost the same as that of TMR.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft Error / FPGA / LUT / TMR / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 342, RECONF2007-43, pp. 1-6, Nov. 2007.
Paper # RECONF2007-43 
Date of Issue 2007-11-15 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2007-43

Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To RECONF 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Designing Soft Error Tolerant LUTs of SRAM-based FPGAs 
Sub Title (in English)  
Keyword(1) Soft Error  
Keyword(2) FPGA  
Keyword(3) LUT  
Keyword(4) TMR  
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1st Author's Name Kohei Satoyama  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Takashi Nakada  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Masaki Nakanishi  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Shigeru Yamashita  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
5th Author's Name Yasuhiko Nakashima  
5th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2007-11-22 09:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2007-43 
Volume (vol) vol.107 
Number (no) no.342 
Page pp.1-6 
#Pages 6 
Date of Issue 2007-11-15 (RECONF) 

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