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Paper Abstract and Keywords
Presentation 2007-12-19 13:30
A Lightweight Fault-tolerant Mechanism for Network-on-Chip
Michihiro Koibuchi (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ), Timothy Mark Pinkston (USC) CPSY2007-42
Abstract (in Japanese) (See Japanese page) 
(in English) Fault tolerance becomes a crucial factor in designing on-chip networks for modern complex chip multiprocessors. In this paper, we propose a lightweight fault-tolerant mechanism called ``default backup path'' (DBP) mainly designed to (1) maintain the network connectivity of a healthy processing element (PE) associated with a faulty router, and (2) avoid disconnecting the network by a large number of faulty routers. In the DBP mechanism, a local channel is directly connected to the channel for
a neighboring router on a router, so that the newly introduced datapaths bypasses various faulty components, such as failed crossbar. The newly introduced datapaths set forms a unidirectional ring topology embedded in the network, such that the unidirectional ring guarantees connectivity to all PEs. Evaluation results show that the DBP mechanism increases by at most 11.3 \% of the amount of additional hardware for a 2-D mesh wormhole network, and its throughput and energy efficiency of the packet transfer between PEs are gracefully degraded, as the number of faults increases.
Keyword (in Japanese) (See Japanese page) 
(in English) Network-on-Chip / on-chip network / reliability / fault tolerance / routing algorithm / deadlock avoidance / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 398, CPSY2007-42, pp. 9-14, Dec. 2007.
Paper # CPSY2007-42 
Date of Issue 2007-12-12 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY  
Conference Date 2007-12-19 - 2007-12-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Campus Plaza Kyoto 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Interconnect technology, etc 
Paper Information
Registration To CPSY 
Conference Code 2007-12-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Lightweight Fault-tolerant Mechanism for Network-on-Chip 
Sub Title (in English)  
Keyword(1) Network-on-Chip  
Keyword(2) on-chip network  
Keyword(3) reliability  
Keyword(4) fault tolerance  
Keyword(5) routing algorithm  
Keyword(6) deadlock avoidance  
Keyword(7)  
Keyword(8)  
1st Author's Name Michihiro Koibuchi  
1st Author's Affiliation National Institute of Informatics (NII)
2nd Author's Name Hiroki Matsutani  
2nd Author's Affiliation Keio University (Keio Univ)
3rd Author's Name Hideharu Amano  
3rd Author's Affiliation Keio University (Keio Univ)
4th Author's Name Timothy Mark Pinkston  
4th Author's Affiliation University of Southern California (USC)
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Speaker Author-1 
Date Time 2007-12-19 13:30:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2007-42 
Volume (vol) vol.107 
Number (no) no.398 
Page pp.9-14 
#Pages 6 
Date of Issue 2007-12-12 (CPSY) 

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