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Paper Abstract and Keywords
Presentation 2007-12-19 09:55
Verification of DPA against XOR in hardware implementation of AES
Yohei Tsuji, Keisuke Iwai, Takakazu Kurokawa (NDA) ISEC2007-113
Abstract (in Japanese) (See Japanese page) 
(in English) DPA techniques against cryptographic devices based on hardware implementation utilize the transition probability of bit signals.
Authors propose a DPA technique using the difference of power consumption between rising transition$(0→1)$ and falling the transition$(1→0)$ of an output signal in CMOS devices.
The result of DPA verification against the XOR operation in Add RoundKey, a part of AES circuit on FPGA, show to be able to specify a part of the private key.
Keyword (in Japanese) (See Japanese page) 
(in English) Side Channel Attack / DPA / XOR / AES / FPGA / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 397, ISEC2007-113, pp. 5-10, Dec. 2007.
Paper # ISEC2007-113 
Date of Issue 2007-12-12 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ISEC2007-113

Conference Information
Committee ISEC  
Conference Date 2007-12-19 - 2007-12-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2007-12-ISEC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Verification of DPA against XOR in hardware implementation of AES 
Sub Title (in English)  
Keyword(1) Side Channel Attack  
Keyword(2) DPA  
Keyword(3) XOR  
Keyword(4) AES  
Keyword(5) FPGA  
Keyword(6)  
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Keyword(8)  
1st Author's Name Yohei Tsuji  
1st Author's Affiliation National Defense Academy (NDA)
2nd Author's Name Keisuke Iwai  
2nd Author's Affiliation National Defense Academy (NDA)
3rd Author's Name Takakazu Kurokawa  
3rd Author's Affiliation National Defense Academy (NDA)
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Speaker Author-1 
Date Time 2007-12-19 09:55:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # ISEC2007-113 
Volume (vol) vol.107 
Number (no) no.397 
Page pp.5-10 
#Pages 6 
Date of Issue 2007-12-12 (ISEC) 

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