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Paper Abstract and Keywords
Presentation 2008-01-16 17:00
A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) VLD2007-115 CPSY2007-58 RECONF2007-61
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, a high-speed string matching circuit for searching a pattern in a given text is proposed. In the circuit, a pattern is specified by a class of restricted regular expressions. The main feature of the proposed hardware, which is distinct from previous string matching circuits, is that a pattern to be retrieved can be set during the execution time. The proposed hardware was implemented on an FPGA chip, and its effectiveness was evaluated.
Keyword (in Japanese) (See Japanese page) 
(in English) string matching / regular expression / FPGA / / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 418, RECONF2007-61, pp. 61-66, Jan. 2008.
Paper # RECONF2007-61 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-115 CPSY2007-58 RECONF2007-61

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation 
Sub Title (in English)  
Keyword(1) string matching  
Keyword(2) regular expression  
Keyword(3) FPGA  
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1st Author's Name Yosuke Kawanaka  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Shin'ichi Wakabayashi  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Shinobu Nagayama  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2008-01-16 17:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2007-115, CPSY2007-58, RECONF2007-61 
Volume (vol) vol.107 
Number (no) no.414(VLD), no.416(CPSY), no.418(RECONF) 
Page pp.61-66 
#Pages 6 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 

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