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Paper Abstract and Keywords
Presentation 2008-01-16 17:25
Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2
Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex) VLD2007-116 CPSY2007-59 RECONF2007-62
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a fast calculation method of the set cover problem, which is implemented on reconfigurable processor DAPDNA-2 of IPFlex Inc. Content replication is a widely employed technique to improve the performance of large-scale content distribution systems. Replica placement method is derived from the set cover problem which is known to be NP-hard. It is difficult to caluculate the large-scale set cover problem on a program counter-based processor. Our proposed algorithm divides the combination optimally and performs pipeline operation.
Experimental results show that the proposed algorithm reduces the execution time by 40 times compared to Intel Pentium 4 2.8GHz.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable processor / DAPDNA-2 / Set Cover Problem / Replica placement / NP-hard / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 418, RECONF2007-62, pp. 67-72, Jan. 2008.
Paper # RECONF2007-62 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-116 CPSY2007-59 RECONF2007-62

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2 
Sub Title (in English)  
Keyword(1) Reconfigurable processor  
Keyword(2) DAPDNA-2  
Keyword(3) Set Cover Problem  
Keyword(4) Replica placement  
Keyword(5) NP-hard  
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1st Author's Name Hiroyuki Ishikawa  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Sho Shimizu  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Yutaka Arakawa  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Naoaki Yamanaka  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Kosuke Shiba  
5th Author's Affiliation IPFlex Inc. (IPFlex)
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Speaker Author-1 
Date Time 2008-01-16 17:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2007-116, CPSY2007-59, RECONF2007-62 
Volume (vol) vol.107 
Number (no) no.414(VLD), no.416(CPSY), no.418(RECONF) 
Page pp.67-72 
#Pages 6 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 

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