Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-02-01 09:50
A High Fidelity Estimation Method for Interconnect Delays with a Ramp Input
Daisuke Orui, Shuji Tsukiyama (Chuo Univ.) CAS2007-96
Abstract (in Japanese) (See Japanese page) 
(in English) With the progress of micro-technologies, the importance of interconnect design has been increasing. Since delays must be estimated repeatedly in the interconnect design, an efficient and high fidelity delay estimation method is indispensable. In this paper, we review estimation methods published so far, and propose a new method which can take input slew into account. The method uses first three moments of admittance and first two moments of transfer function, and solves the voltage waveform of a sink by using RC 2 ladder circuit. Experimental results show that the variation of the absolutes of relative errors of estimated delays to nodes are reduced from the previous methods, and hence the fidelity is increased.
Keyword (in Japanese) (See Japanese page) 
(in English) interconnect delay / delay estimation / input slew / fidelity / RC 2 ladder circuit / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 476, CAS2007-96, pp. 13-18, Jan. 2008.
Paper # CAS2007-96 
Date of Issue 2008-01-25 (CAS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2007-96

Conference Information
Committee CAS  
Conference Date 2008-01-31 - 2008-02-01 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CAS 
Conference Code 2008-01-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A High Fidelity Estimation Method for Interconnect Delays with a Ramp Input 
Sub Title (in English)  
Keyword(1) interconnect delay  
Keyword(2) delay estimation  
Keyword(3) input slew  
Keyword(4) fidelity  
Keyword(5) RC 2 ladder circuit  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Daisuke Orui  
1st Author's Affiliation Chuo University (Chuo Univ.)
2nd Author's Name Shuji Tsukiyama  
2nd Author's Affiliation Chuo University (Chuo Univ.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2008-02-01 09:50:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2007-96 
Volume (vol) vol.107 
Number (no) no.476 
Page pp.13-18 
#Pages 6 
Date of Issue 2008-01-25 (CAS) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan