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Paper Abstract and Keywords
Presentation 2008-02-01 10:55
A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation
Tsutomu Ishida, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-98
Abstract (in Japanese) (See Japanese page) 
(in English) In VLSI design, circuits are improved by circuit modifications.The minimum feasible clock period of a circuit is one of the most important factor in circuit evaluation.Since circuit modifications are repeated in the circuit synthesis, it is very important to speed up the calculation of the minimum feasible clock period.With every circuit modification, the minimum feasible clock period in generalized synchronous framework is calculated by constructing the shortest path tree of the constraint graph of the circuit.In this paper, we propose a minimum feasible clock period determination algorithm for circuit modification which uses a fast modification algorithm for shortest path tree.Proposed modification algorithm constructs a shortest path tree of the modified circuit from the shortest path tree of the previous circuit.Proposed determination algorithm calculates the minimum feasible clock period of the modified circuit efficiently by applying proposed modification algorithm.In experiments, we show that proposed determination algorithm calculates the minimum feasible clock period of the modified circuit faster than existing methods.
Keyword (in Japanese) (See Japanese page) 
(in English) generalized synchronous framework / minimum clock period / circuit modification / shortest path tree / modification algorithm / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 476, CAS2007-98, pp. 25-30, Jan. 2008.
Paper # CAS2007-98 
Date of Issue 2008-01-25 (CAS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2007-98

Conference Information
Committee CAS  
Conference Date 2008-01-31 - 2008-02-01 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To CAS 
Conference Code 2008-01-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation 
Sub Title (in English)  
Keyword(1) generalized synchronous framework  
Keyword(2) minimum clock period  
Keyword(3) circuit modification  
Keyword(4) shortest path tree  
Keyword(5) modification algorithm  
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1st Author's Name Tsutomu Ishida  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Yukihide Kohira  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2008-02-01 10:55:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2007-98 
Volume (vol) vol.107 
Number (no) no.476 
Page pp.25-30 
#Pages 6 
Date of Issue 2008-01-25 (CAS) 

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