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Paper Abstract and Keywords
Presentation 2008-03-28 08:45
A Hardware Acceleration for Semi-Formal Model Checking
Satoshi Morishita, Hiroaki Yoshida, Masahiro Fujita (Univ of Tokyo) DC2007-103 CPSY2007-99
Abstract (in Japanese) (See Japanese page) 
(in English) The verification becomes important now as the design becomes complex and large-scale.Model checking which is one of the most important verification has been held back by the state explosion problem, which is the problem that the number of states grows exponentially in the number of system components.So we propose an efficient model checking method in this paper.We have enhanced a semi-formal bounded model checking by using a hardware accelerator and modified the codes to be easily implemented on a hardware.The experimental results with some examples show that the proposed method can execute model checking in short time.
Keyword (in Japanese) (See Japanese page) 
(in English) Model Checking / / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 559, DC2007-103, pp. 115-120, March 2008.
Paper # DC2007-103 
Date of Issue 2008-03-20 (DC, CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB  
Conference Date 2008-03-27 - 2008-03-28 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2008-03-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Hardware Acceleration for Semi-Formal Model Checking 
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Keyword(1) Model Checking  
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1st Author's Name Satoshi Morishita  
1st Author's Affiliation University of Tokyo (Univ of Tokyo)
2nd Author's Name Hiroaki Yoshida  
2nd Author's Affiliation University of Tokyo (Univ of Tokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation University of Tokyo (Univ of Tokyo)
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Speaker Author-1 
Date Time 2008-03-28 08:45:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # DC2007-103, CPSY2007-99 
Volume (vol) vol.107 
Number (no) no.559(DC), no.558(CPSY) 
Page pp.115-120 
#Pages 6 
Date of Issue 2008-03-20 (DC, CPSY) 

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