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Paper Abstract and Keywords
Presentation 2008-04-17 11:15
[Invited Talk] An 833MHz Pseudo Two-Port Embedded DRAM for Graphics Applications
Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka (Toshiba) ICD2008-3
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a pseudo two-port embedded DRAM macro developed for graphics applications. It introduces read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS) for enabling concurrent read/write operation in two different banks. A 32Mbit macro is characterized via a test chip fabricated in a 65nm embedded DRAM process. 833MHz of the page mode operation frequency at 1.2V is confirmed.
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded DRAM / Pseudo Two-port / Graphics Application / Concurrent Read/Write / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 6, ICD2008-3, pp. 13-18, April 2008.
Paper # ICD2008-3 
Date of Issue 2008-04-10 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2008-04-17 - 2008-04-18 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An 833MHz Pseudo Two-Port Embedded DRAM for Graphics Applications 
Sub Title (in English)  
Keyword(1) Embedded DRAM  
Keyword(2) Pseudo Two-port  
Keyword(3) Graphics Application  
Keyword(4) Concurrent Read/Write  
Keyword(5)  
Keyword(6)  
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Keyword(8)  
1st Author's Name Mariko Kaku  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Hitoshi Iwai  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name Takeshi Nagai  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
4th Author's Name Masaharu Wada  
4th Author's Affiliation Toshiba Corporation (Toshiba)
5th Author's Name Atsushi Suzuki  
5th Author's Affiliation Toshiba Corporation (Toshiba)
6th Author's Name Tomohisa Takai  
6th Author's Affiliation Toshiba Corporation (Toshiba)
7th Author's Name Naoko Itoga  
7th Author's Affiliation Toshiba Corporation (Toshiba)
8th Author's Name Takayuki Miyazaki  
8th Author's Affiliation Toshiba Corporation (Toshiba)
9th Author's Name Takayuki Iwai  
9th Author's Affiliation Toshiba Corporation (Toshiba)
10th Author's Name Hiroyuki Takenaka  
10th Author's Affiliation Toshiba Microelectronics Corporation (Toshiba Microelectronics)
11th Author's Name Takehiko Hojo  
11th Author's Affiliation Toshiba Corporation (Toshiba)
12th Author's Name Shinji Miyano  
12th Author's Affiliation Toshiba Corporation (Toshiba)
13th Author's Name Nobuaki Otsuka  
13th Author's Affiliation Toshiba Corporation (Toshiba)
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Speaker Author-1 
Date Time 2008-04-17 11:15:00 
Presentation Time 50 minutes 
Registration for ICD 
Paper # ICD2008-3 
Volume (vol) vol.108 
Number (no) no.6 
Page pp.13-18 
#Pages 6 
Date of Issue 2008-04-10 (ICD) 

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