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Paper Abstract and Keywords
Presentation 2008-04-18 14:20
A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-13
Abstract (in Japanese) (See Japanese page) 
(in English) A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-um standard CMOS process with 1.5V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-um2 bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded MRAMs / High-speed MRAM / 2T1MTJ cell structure / Half-pitch-shift arrangement / Multi-divided bitline architecture / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 6, ICD2008-13, pp. 69-74, April 2008.
Paper # ICD2008-13 
Date of Issue 2008-04-10 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2008-04-17 - 2008-04-18 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture 
Sub Title (in English)  
Keyword(1) Embedded MRAMs  
Keyword(2) High-speed MRAM  
Keyword(3) 2T1MTJ cell structure  
Keyword(4) Half-pitch-shift arrangement  
Keyword(5) Multi-divided bitline architecture  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Noboru Sakimura  
1st Author's Affiliation NEC Corporation (NEC)
2nd Author's Name Tadahiko Sugibayashi  
2nd Author's Affiliation NEC Corporation (NEC)
3rd Author's Name Ryusuke Nebashi  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Hiroaki Honjo  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Shinsaku Saito  
5th Author's Affiliation NEC Corporation (NEC)
6th Author's Name Yuko Kato  
6th Author's Affiliation NEC Corporation (NEC)
7th Author's Name Naoki Kasai  
7th Author's Affiliation NEC Corporation (NEC)
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Speaker Author-1 
Date Time 2008-04-18 14:20:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2008-13 
Volume (vol) vol.108 
Number (no) no.6 
Page pp.69-74 
#Pages 6 
Date of Issue 2008-04-10 (ICD) 

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