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Paper Abstract and Keywords
Presentation 2008-06-20 16:15
Transistor Aging and Operational Environment of Logic Circuits
Masafumi Haraguchi (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.) DC2008-17
Abstract (in Japanese) (See Japanese page) 
(in English) With the progress of integrated circuit technology, it is becoming important to consider circuit aging. In this work we evaluate influence on circuit characteristic for the operational environment and circuit variation by a circuit simulator, as a preparation of aging detection. At first, for a ring oscillator which can be used as a process monitor circuit, we investigate frequency change for changes of temperature and power supply voltage, respectively. Then we examine delay of a circuit consisting of NOT gates by changing the power supply voltage and temperature change. In addition, assuming the aging transistors by NBTI, we investigate the change of circuit delay.
Keyword (in Japanese) (See Japanese page) 
(in English) Logic circuit / Circuit simulation / Negative bias temperature instability / Reliability / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 99, DC2008-17, pp. 35-40, June 2008.
Paper # DC2008-17 
Date of Issue 2008-06-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2008-06-20 - 2008-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification 
Paper Information
Registration To DC 
Conference Code 2008-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Transistor Aging and Operational Environment of Logic Circuits 
Sub Title (in English)  
Keyword(1) Logic circuit  
Keyword(2) Circuit simulation  
Keyword(3) Negative bias temperature instability  
Keyword(4) Reliability  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masafumi Haraguchi  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
2nd Author's Name Yukiya Miura  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
3rd Author's Name Seiji Kajihara  
3rd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
4th Author's Name Yasuo Sato  
4th Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
5th Author's Name Kohei Miyase  
5th Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
6th Author's Name Xiaoqing Wen  
6th Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
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Speaker Author-1 
Date Time 2008-06-20 16:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2008-17 
Volume (vol) vol.108 
Number (no) no.99 
Page pp.35-40 
#Pages 6 
Date of Issue 2008-06-13 (DC) 

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