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| Presentation | 2008-06-27 09:40 An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST)  CAS2008-21 VLD2008-34 SIP2008-55 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Information on false paths in a circuit is useful for design and test. The use of this information may contribute not only in reducing the time required for logic synthesis, the area, the test generation time and the test application time of the circuit but also in alleviating the over-testing. Since identification of false paths at gate-level is hard for large circuits with huge number of paths, several methods using high-level design information, e.g. register transfer level (RTL) structural information or high-level synthesis information, have been proposed. These methods are effective only if the correspondence between paths at RTL and those at gate-level is available. Until now, the correspondence has been established only by module interface preserving-logic synthesis. In this paper, we propose a method of mapping an RTL path to the gate-level paths without restricting the logic synthesis. The method first maps each bit slice RTL signal line of an RTL path to a gate level signal line by considering the functional equivalence of those signal lines. Then the RTL path are mapped to gate level paths using these correspondences. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | path mapping / register transfer level / gate-level / functional equivalence / fault diagnosis / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 107, VLD2008-34, pp. 13-18, June 2008. | |
| Paper # | VLD2008-34 | |
| Date of Issue | 2008-06-20 (CAS, VLD, SIP) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2008-21 VLD2008-34 SIP2008-55 |
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| Conference Information | |
| Committee | VLD CAS SIP |
| Conference Date | 2008-06-26 - 2008-06-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-06-VLD-CAS-SIP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to RTL-GL Path Mapping Based on Functional Equivalence |
| Sub Title (in English) | |
| Keyword(1) | path mapping |
| Keyword(2) | register transfer level |
| Keyword(3) | gate-level |
| Keyword(4) | functional equivalence |
| Keyword(5) | fault diagnosis |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroshi Iwata |
| 1st Author's Affiliation | NARA INSTITUTE of SCIENCE and TECHNOLOGY (NAIST) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | NARA INSTITUTE of SCIENCE and TECHNOLOGY (NAIST) |
| 3rd Author's Name | Hideo Fujiwara |
| 3rd Author's Affiliation | NARA INSTITUTE of SCIENCE and TECHNOLOGY (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2008-06-27 09:40:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | CAS2008-21, VLD2008-34, SIP2008-55 |
| Volume (vol) | vol.108 |
| Number (no) | no.105(CAS), no.107(VLD), no.109(SIP) |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2008-06-20 (CAS, VLD, SIP) |
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