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| 講演名 | 2008-07-10 10:15 Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering(GIBL) ○Seongjae Cho・Il Han Park・Jung Hoon Lee・Gil Sung Lee・Jong Duk Lee・Hyungcheol Shin・Byung-Gook Park（Seoul National Univ.）  ED2008-58 SDM2008-77 |
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| 抄録 | （和） | Recently, various 3-D nonvolatile memory (NVM) devices have been researched for improving the degree of integration. NVM device of pillar structure can be considered as a candidate. When this is applied to NAND flash memory array, one end of the device channel is connected to the bulk silicon. At this time, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that possibly occurs in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which shall be criteria in the implementation of reliable ultra-small NVM devices. |
| （英） | Recently, various 3-D nonvolatile memory (NVM) devices have been researched for improving the degree of integration. NVM device of pillar structure can be considered as a candidate. When this is applied to NAND flash memory array, one end of the device channel is connected to the bulk silicon. At this time, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that possibly occurs in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which shall be criteria in the implementation of reliable ultra-small NVM devices. | |
| キーワード | （和） | 3-D nonvolatile memory / NAND flash memory array / saturation current / channel potential barrier / gate-induced barrier lowering (GIBL) / / / |
| （英） | 3-D nonvolatile memory / NAND flash memory array / saturation current / channel potential barrier / gate-induced barrier lowering (GIBL) / / / | |
| 文献情報 | 信学技報, vol. 108, no. 122, SDM2008-77, pp. 95-99, 2008年7月. | |
| 資料番号 | SDM2008-77 | |
| 発行日 | 2008-07-02 (ED, SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| 著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します．(許諾番号：10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| PDFダウンロード | ED2008-58 SDM2008-77 |
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