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Paper Abstract and Keywords
Presentation 2008-07-11 13:50
Study on Gate Around Transistor (GAT) Layout for Radiation Hardness
Min-su Lee, Young-Soo Lee, Chul-Bum Kim, Young-Ho Kim (KAIST), Byoung-Gon Yu, Hee Chul Lee (ETRI) ED2008-91 SDM2008-110
Abstract (in Japanese) (See Japanese page) 
(in English) We designed a Gate Around Transistor (GAT) layout for radiation hardness. A GAT MOSFET layout with an improved guard ring structure has been fabricated. The Vg-Id and Vd-Id curves are measured before and after exposure to 1Mrad gamma (・? radiation with a 250krad/hr dose rate. The GAT layout structure shows immunity to radiation. The Vg-Id curve is almost unchanged and leakage current is slightly increased. The effective W/L ratio of the GAT layout is measured and simulated. The GAT layout structure is applied to a source follower schematic. Characteristics of the source follower are measured before and after exposure to 1Mrad gamma (・? radiation with a 250krad/hr dose rate. Characteristics of the source follower are almost unchanged. A chip was fabricated using commercial 0.35 micron CMOS technology.
Keyword (in Japanese) (See Japanese page) 
(in English) Gate Around Transistor layout / GAT / Radiation hardness / Radiation Hardening By Design / RHBD / 0.35 micorn CMOS technology / STI oxide / Leakage current  
Reference Info. IEICE Tech. Rep., vol. 108, no. 122, SDM2008-110, pp. 275-280, July 2008.
Paper # SDM2008-110 
Date of Issue 2008-07-02 (ED, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SDM ED  
Conference Date 2008-07-09 - 2008-07-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kaderu２・７ 
Topics (in Japanese) (See Japanese page) 
Topics (in English) 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices 
Paper Information
Registration To SDM 
Conference Code 2008-07-SDM-ED 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study on Gate Around Transistor (GAT) Layout for Radiation Hardness 
Sub Title (in English)  
Keyword(1) Gate Around Transistor layout  
Keyword(2) GAT  
Keyword(3) Radiation hardness  
Keyword(4) Radiation Hardening By Design  
Keyword(5) RHBD  
Keyword(6) 0.35 micorn CMOS technology  
Keyword(7) STI oxide  
Keyword(8) Leakage current  
1st Author's Name Min-su Lee  
1st Author's Affiliation Korea Advanced Institute of Science and Technology (KAIST)
2nd Author's Name Young-Soo Lee  
2nd Author's Affiliation Korea Advanced Institute of Science and Technology (KAIST)
3rd Author's Name Chul-Bum Kim  
3rd Author's Affiliation Korea Advanced Institute of Science and Technology (KAIST)
4th Author's Name Young-Ho Kim  
4th Author's Affiliation Korea Advanced Institute of Science and Technology (KAIST)
5th Author's Name Byoung-Gon Yu  
5th Author's Affiliation Electronics and Telecommunications Research Institute (ETRI)
6th Author's Name Hee Chul Lee  
6th Author's Affiliation Electronics and Telecommunications Research Institute (ETRI)
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Speaker Author-1 
Date Time 2008-07-11 13:50:00 
Presentation Time 15 minutes 
Registration for SDM 
Paper # ED2008-91, SDM2008-110 
Volume (vol) vol.108 
Number (no) no.121(ED), no.122(SDM) 
Page pp.275-280 
#Pages 6 
Date of Issue 2008-07-02 (ED, SDM) 

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