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Presentation 2008-10-23 16:05
[Panel Discussion] Challenges and Future of Analog Circuit Design using Sub-100nm CMOS Devices
Shoji Kawahito (Shizuoka Univ.), Shigetoshi Sugawa (Tohoku Univ.), Tatsuya Ohguro (Toshiba), Hidetoshi Onodera (Kyoto Univ.), Kunihiko Goto (Fujitsu Labs.), Toshihiko Hamasaki (TI), Shiro Dosho (Panasonic)
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Conference Information
Committee ICD ITE-IST  
Conference Date 2008-10-22 - 2008-10-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University 
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Paper Information
Registration To ICD 
Conference Code 2008-10-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Challenges and Future of Analog Circuit Design using Sub-100nm CMOS Devices 
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1st Author's Name Shoji Kawahito  
1st Author's Affiliation Shizuoka University (Shizuoka Univ.)
2nd Author's Name Shigetoshi Sugawa  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Tatsuya Ohguro  
3rd Author's Affiliation Toshiba (Toshiba)
4th Author's Name Hidetoshi Onodera  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
5th Author's Name Kunihiko Goto  
5th Author's Affiliation Fujitsu Laboratories (Fujitsu Labs.)
6th Author's Name Toshihiko Hamasaki  
6th Author's Affiliation TI (TI)
7th Author's Name Shiro Dosho  
7th Author's Affiliation Panasonic (Panasonic)
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Date Time 2008-10-23 16:05:00 
Presentation Time 90 minutes 
Registration for ICD 
Paper #  
Volume (vol) vol.108 
Number (no) no.253 
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