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Paper Abstract and Keywords
Presentation 2008-10-24 11:15
Reconfigurable Hardware Architecture for Power Saving Sensor Node with Function Specialization
Satoshi Tanaka (Kobe Univ.), Yutaka Yanagisawa (NTT), Tsutomu Terada, Masahiko Tsukamoto (Kobe Univ.) USN2008-58
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a reconfigurable hardware architecture to reduce the power consumption of
a small sensor node that has both various types of sensors and wireless communication facility, achieved by an
adaptive function specialization mechanism. Traditional sensor nodes must have had a powerful and multifunctional
MCU (Micro- Controller Unit) to satisfy requirements for processing any kinds of applications. However,
such an MCU often consumes much power for unused circuits. To avoid this situation, we propose a reconfigurable
architecture based on FPGA (Field Programmable Gate Array) instead of MCU because FPGA can dynamically
change the circuit to the optimal one that is just used for the calculation required by an application. Moreover,
we implemented a prototype system to do a preliminary evaluation of our proposed mechanism. In this evaluation,
we show the performance of our proposed reconfigurable architecture by comparison with traditional architecture
using processing time and power consumption. The experimental result shows that our proposed mechanism has
the ability to reduce power of sensor nodes to prolong the lifetime of nodes without decreasing the processing time.
Keyword (in Japanese) (See Japanese page) 
(in English) Sensor Networks / Reconfigurable Hardware / Saving Power Consumption / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 252, USN2008-58, pp. 117-122, Oct. 2008.
Paper # USN2008-58 
Date of Issue 2008-10-15 (USN) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF USN2008-58

Conference Information
Committee SR RCS USN AN  
Conference Date 2008-10-22 - 2008-10-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa industry support center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Wireless discributed network special session and general session 
Paper Information
Registration To USN 
Conference Code 2008-10-SR-RCS-USN-AN 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reconfigurable Hardware Architecture for Power Saving Sensor Node with Function Specialization 
Sub Title (in English)  
Keyword(1) Sensor Networks  
Keyword(2) Reconfigurable Hardware  
Keyword(3) Saving Power Consumption  
Keyword(4)  
Keyword(5)  
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Keyword(8)  
1st Author's Name Satoshi Tanaka  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Yutaka Yanagisawa  
2nd Author's Affiliation NTT Communication Science Laboratories (NTT)
3rd Author's Name Tsutomu Terada  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Masahiko Tsukamoto  
4th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2008-10-24 11:15:00 
Presentation Time 20 minutes 
Registration for USN 
Paper # USN2008-58 
Volume (vol) vol.108 
Number (no) no.252 
Page pp.117-122 
#Pages 6 
Date of Issue 2008-10-15 (USN) 

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