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Paper Abstract and Keywords
Presentation 2008-10-24 12:30
All digital PLL with independent loop characteristic by using fine clock-period comparator
Yukinobu Makihara, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.) ICD2008-87
Abstract (in Japanese) (See Japanese page) 
(in English) We proposed new architecture of phase-locked loop (PLL) by using clock-period comparison. For a digitally controlled PLL without a loop filter, we evaluated the use of a clock-period comparator (CPC). In proposed PLL, only the frequency lock operation should be performed; however, when the phases of the reference signal and the output signal approach each other, the frequency control by CPC results in the phase lock operation. Thus, the phase lock operation is also simultaneously achieved. The transfer function of proposed PLL can be derived at the frequency domain. Therefore, the lock operation is achieved following the response of a first order control system. The theoretical analysis of a phase-lock mechanism, a lock-up time, and spurious noise is discussed and confirmed through system simulation.
We designed element blocks of the proposed PLL using a 0.25-μm CMOS process. The voltage controlled oscillator (VCO) was replaced with a digitally controlled oscillator (DCO). The DCO consists of digital current controller and current controlled oscillator. As for the frequency characteristics of the DCO, secondary nonlinearity appears because the I−V characteristics of the MOSFET have secondary nonlinearity. To compensate of this, two-stage current controller was implemanted. We also confirmed a phase lock operation through SPICE simulation of the MOSFET level.
Keyword (in Japanese) (See Japanese page) 
(in English) PLL / DCO / ADPLL / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 253, ICD2008-87, pp. 165-170, Oct. 2008.
Paper # ICD2008-87 
Date of Issue 2008-10-15 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD ITE-IST  
Conference Date 2008-10-22 - 2008-10-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-10-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) All digital PLL with independent loop characteristic by using fine clock-period comparator 
Sub Title (in English)  
Keyword(1) PLL  
Keyword(2) DCO  
Keyword(3) ADPLL  
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1st Author's Name Yukinobu Makihara  
1st Author's Affiliation Hokkaido University (Hokkaido Univ.)
2nd Author's Name Masayuki Ikebe  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ.)
3rd Author's Name Junichi Motohisa  
3rd Author's Affiliation Hokkaido University (Hokkaido Univ.)
4th Author's Name Eiichi Sano  
4th Author's Affiliation Hokkaido University (Hokkaido Univ.)
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Speaker Author-1 
Date Time 2008-10-24 12:30:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2008-87 
Volume (vol) vol.108 
Number (no) no.253 
Page pp.165-170 
#Pages 6 
Date of Issue 2008-10-15 (ICD) 

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