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| Presentation | 2008-10-31 14:30 Optimization method of data communication PEs for Massively Parallel SIMD processor Sumio Hirota, Akihiro Kodama, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  CPSY2008-33 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The MX core is a massively parallel SIMD (Single Instruction Multiple Data) processor based on fine-grained 1,024 PEs (Processing Elements). This is developed by Renesas technology corp., achieves high performance for multimedia processing. However,The data communication between PEs is regularly,so all data only move same direction and distance. This is factor of the lower performance.This paper describes a path planning efficiency method for SIMD controlled data communication with MX core architecture. We evaluate the communication frequencies of each different number of data using some data communication patterns. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | MX core / SIMD / data communication / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 273, CPSY2008-33, pp. 23-28, Oct. 2008. | |
| Paper # | CPSY2008-33 | |
| Date of Issue | 2008-10-24 (CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2008-33 |
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| Conference Information | |
| Committee | CPSY |
| Conference Date | 2008-10-31 - 2008-10-31 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiroshima City Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Advanced Computer System Technologies, etc. |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2008-10-CPSY |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization method of data communication PEs for Massively Parallel SIMD processor |
| Sub Title (in English) | |
| Keyword(1) | MX core |
| Keyword(2) | SIMD |
| Keyword(3) | data communication |
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| 1st Author's Name | Sumio Hirota |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Akihiro Kodama |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Masahiro Iida |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Toshinori Sueyoshi |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-10-31 14:30:00 |
| Presentation Time | 30 minutes |
| Registration for | CPSY |
| Paper # | CPSY2008-33 |
| Volume (vol) | vol.108 |
| Number (no) | no.273 |
| Page | pp.23-28 |
| #Pages | 6 |
| Date of Issue | 2008-10-24 (CPSY) |
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