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Paper Abstract and Keywords
Presentation 2008-11-17 14:15
Analysis of Open Fault using TEG Chip
Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) VLD2008-63 DC2008-31
Abstract (in Japanese) (See Japanese page) 
(in English) The high integration of the semiconductor technology advances, and the fault detection and the failure diagnosis of LSI become difficult. Especially, a practicable modeling of an open fault has not been performed yet, though measures against the open fault become important more with advancement of LSI process technology. So, we have fabricated TEG (Test Element Group) chips into which open defects is intentionally built, and then we research on modeling the open fault based on the measurement data of the TEG chips. In this paper, the measurement data of the TEG chip is analyzed, and we report how influence a logical value of a faulty signal line with full open defect actually depend on those of the adjacent signal lines in the real chip.
Keyword (in Japanese) (See Japanese page) 
(in English) open faults / TEG chip / LSI testing / fault model / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 299, DC2008-31, pp. 19-24, Nov. 2008.
Paper # DC2008-31 
Date of Issue 2008-11-10 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-63 DC2008-31

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To DC 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Open Fault using TEG Chip 
Sub Title (in English)  
Keyword(1) open faults  
Keyword(2) TEG chip  
Keyword(3) LSI testing  
Keyword(4) fault model  
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1st Author's Name Toshiyuki Tsutsumi  
1st Author's Affiliation Meiji University (Meiji Univ)
2nd Author's Name Yasuyuki Kariya  
2nd Author's Affiliation Meiji University (Meiji Univ)
3rd Author's Name Koji Yamazaki  
3rd Author's Affiliation Meiji University (Meiji Univ)
4th Author's Name Masaki Hashizume  
4th Author's Affiliation Tokushima University (Tokushima Univ)
5th Author's Name Hiroyuki Yotsuyanagi  
5th Author's Affiliation Tokushima University (Tokushima Univ)
6th Author's Name Hiroshi Takahashi  
6th Author's Affiliation Ehime University (Ehime Univ)
7th Author's Name Yoshinobu Higami  
7th Author's Affiliation Ehime University (Ehime Univ)
8th Author's Name Yuzo Takamatsu  
8th Author's Affiliation Ehime University (Ehime Univ)
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Speaker Author-2 
Date Time 2008-11-17 14:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2008-63, DC2008-31 
Volume (vol) vol.108 
Number (no) no.298(VLD), no.299(DC) 
Page pp.19-24 
#Pages 6 
Date of Issue 2008-11-10 (VLD, DC) 

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