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Paper Abstract and Keywords
Presentation 2009-01-23 10:20
Acceleration of CIP Method with the Time and Space Pipeline in FPGA Implementation
Sho Endo, Jun Sonoda (SNCT), Motoyuki Sato (Tohoku Universtiy) AP2008-177
Abstract (in Japanese) (See Japanese page) 
(in English) We have proposed a new hardware algorithm named the Time and Space Pipeline(TSP), and have shown that the TSP can compute faster than conventional parallel computing. On the other hand, CIP method which have proposed as a method of electromagnetic field analysis. The CIP method has high accuracy and isexpected that has lower computation cost than FDTD method at the same accuracy. We have implemented one-dimensional CIP method in FPGA, and have shown that the CIP method with the TSP has lower cost than CIP method on PC and FDTD method implemented in FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) the TSP / CIP method / FDTD method / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 386, AP2008-177, pp. 157-161, Jan. 2009.
Paper # AP2008-177 
Date of Issue 2009-01-14 (AP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF AP2008-177

Conference Information
Committee AP  
Conference Date 2009-01-21 - 2009-01-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Fukuoka University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Etc. 
Paper Information
Registration To AP 
Conference Code 2009-01-AP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Acceleration of CIP Method with the Time and Space Pipeline in FPGA Implementation 
Sub Title (in English)  
Keyword(1) the TSP  
Keyword(2) CIP method  
Keyword(3) FDTD method  
Keyword(4) FPGA  
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1st Author's Name Sho Endo  
1st Author's Affiliation Sendai National College of Technology (SNCT)
2nd Author's Name Jun Sonoda  
2nd Author's Affiliation Sendai National College of Technology (SNCT)
3rd Author's Name Motoyuki Sato  
3rd Author's Affiliation Tohoku Universtiy (Tohoku Universtiy)
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Speaker Author-1 
Date Time 2009-01-23 10:20:00 
Presentation Time 25 minutes 
Registration for AP 
Paper # AP2008-177 
Volume (vol) vol.108 
Number (no) no.386 
Page pp.157-161 
#Pages 5 
Date of Issue 2009-01-14 (AP) 

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