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| Presentation | 2009-01-29 14:45 A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length Shohei Hashimoto, Yuta Totsuka, Masamichi Makino, Hikaru Yasuda, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.)  VLD2008-102 CPSY2008-64 RECONF2008-66 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose a computer architecture for numbers of arbitrary word length with unlimited processing data length. In this design, we developed some original calculation methods using the clocks with different frequencies, and the multi-bus system for efficient processing and speedup. Two ALUs with different word length are also for the same purpose. We carried out experiments on a prototype system on FPGA and confirmed the proper behavior. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | numbers of arbitrary word length / multi-bus system / computer architecture / scalable operation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 413, CPSY2008-64, pp. 63-68, Jan. 2009. | |
| Paper # | CPSY2008-64 | |
| Date of Issue | 2009-01-22 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2008-102 CPSY2008-64 RECONF2008-66 |
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| Conference Information | |
| Committee | VLD CPSY RECONF IPSJ-SLDM |
| Conference Date | 2009-01-29 - 2009-01-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2009-01-VLD-CPSY-RECONF-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length |
| Sub Title (in English) | |
| Keyword(1) | numbers of arbitrary word length |
| Keyword(2) | multi-bus system |
| Keyword(3) | computer architecture |
| Keyword(4) | scalable operation |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Shohei Hashimoto |
| 1st Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 2nd Author's Name | Yuta Totsuka |
| 2nd Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 3rd Author's Name | Masamichi Makino |
| 3rd Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 4th Author's Name | Hikaru Yasuda |
| 4th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 5th Author's Name | Tsugio Nakamura |
| 5th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 6th Author's Name | Narito Fuyutsume |
| 6th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 7th Author's Name | Hiroshi Kasahara |
| 7th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-01-29 14:45:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | VLD2008-102, CPSY2008-64, RECONF2008-66 |
| Volume (vol) | vol.108 |
| Number (no) | no.412(VLD), no.413(CPSY), no.414(RECONF) |
| Page | pp.63-68 |
| #Pages | 6 |
| Date of Issue | 2009-01-22 (VLD, CPSY, RECONF) |
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