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Paper Abstract and Keywords
Presentation 2009-01-30 10:30
A study for accurate RTL timing modeling
Shota Nakajima, Masahiro Fukui (Ritsumeikan Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Recent, due to the rapid progress of LSI technology, efficient and low-power designs have been highly required to keep high performance. To satisfy these requests, it is very important to be able to explore the value of power and delay at a high-level early in the design process. This paper proposes a new efficient RTL delay macro-model to address these recent problems. The goal is to provide transistor-level accuracy at the RTL with Vt and Vdd variability. The Modeling algorithm that considers parasitic capacitances and experimental results are discussed.
Keyword (in Japanese) (See Japanese page) 
(in English) delaymacromodel / / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, pp. 129-134, Jan. 2009.
Paper #  
Date of Issue 2009-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Conference Information
Committee VLD CPSY RECONF IPSJ-SLDM  
Conference Date 2009-01-29 - 2009-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To IPSJ-SLDM 
Conference Code 2009-01-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A study for accurate RTL timing modeling 
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1st Author's Name Shota Nakajima  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Masahiro Fukui  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2009-01-30 10:30:00 
Presentation Time 25 minutes 
Registration for IPSJ-SLDM 
Paper # VLD2008-113, CPSY2008-75, RECONF2008-77 
Volume (vol) vol.108 
Number (no) no.412(VLD), no.413(CPSY), no.414(RECONF) 
Page pp.129-134 
#Pages
Date of Issue 2009-01-22 (VLD, CPSY, RECONF) 


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