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Paper Abstract and Keywords
Presentation 2009-03-06 10:00
Design and implementation of prefetch mechanism for exploiting data-level parallelism
Yusuke Murata, Kazutoshi Suito, Nobuyuki Yamasaki (Keio Univ.) CPSY2008-98 DC2008-89
Abstract (in Japanese) (See Japanese page) 
(in English) As the architecture for performing multimedia processing at high speed,
a SIMD computing unit and a vector operation machine are mentioned.
In those architecure, the same processing can be simultaneously performed to two or more
data. But a memory is a low speed as compared with a processor,
the performance of processing unit is limited. In this paper,
the address accessed the next from the memory access pattern of multimedia processing is predicted, and the technique of reducing a memory access latency by performing prefetch is proposed. A result of evaluating using a part of DENBench of EEMBC shows improvement in IPC.
Keyword (in Japanese) (See Japanese page) 
(in English) Prefetch / Stride / Vector / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 464, DC2008-89, pp. 61-66, March 2009.
Paper # DC2008-89 
Date of Issue 2009-02-26 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2008-98 DC2008-89

Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB  
Conference Date 2009-03-05 - 2009-03-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Sado Island Integrated Development Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2009 
Paper Information
Registration To DC 
Conference Code 2009-03-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and implementation of prefetch mechanism for exploiting data-level parallelism 
Sub Title (in English)  
Keyword(1) Prefetch  
Keyword(2) Stride  
Keyword(3) Vector  
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1st Author's Name Yusuke Murata  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Kazutoshi Suito  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Nobuyuki Yamasaki  
3rd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2009-03-06 10:00:00 
Presentation Time 30 minutes 
Registration for DC 
Paper # CPSY2008-98, DC2008-89 
Volume (vol) vol.108 
Number (no) no.463(CPSY), no.464(DC) 
Page pp.61-66 
#Pages 6 
Date of Issue 2009-02-26 (CPSY, DC) 

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