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Paper Abstract and Keywords
Presentation 2009-03-11 16:15
A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits
Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135
Abstract (in Japanese) (See Japanese page) 
(in English) In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously,
circuit performances are expected to be improved. For enough performance improvement, logic circuit synthesis method in general-synchronous framework is demanded. The purpose of this work is to develop a delay insertion method that realizes the maximum circuit performance in general synchronous framework by the minimum amount of inserted delays under the assumption that any clock schedule is realized by an deal clock distribution circuit. In this paper, we prove that the problem in which the amount of inserted delays is minimized is NP-hard. Then, we propose a new heuristic delay insertion method that can apply to large-scale circuits.
In experiments, we evaluated the proposed method.
Keyword (in Japanese) (See Japanese page) 
(in English) General-synchronous circuits / Delay insertion / Clock scheduling / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-135, pp. 53-58, March 2009.
Paper # VLD2008-135 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-135

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits 
Sub Title (in English)  
Keyword(1) General-synchronous circuits  
Keyword(2) Delay insertion  
Keyword(3) Clock scheduling  
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1st Author's Name Shuhei Tani  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Yukihide Kohira  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker Author-1 
Date Time 2009-03-11 16:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-135 
Volume (vol) vol.108 
Number (no) no.478 
Page pp.53-58 
#Pages 6 
Date of Issue 2009-03-04 (VLD) 

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