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Paper Abstract and Keywords
Presentation 2009-03-12 13:50
A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC
Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-147
Abstract (in Japanese) (See Japanese page) 
(in English) An on-chip bus architecture is utilized as a communication architecture of a System-on-a-Chip.
It is difficult to increase a bus clock frequency because of a wiring delays.
High-performance on-chip communication architecture is demanded.
Network-on-Chip (NoC) is one of on-chip communication architectures, an alternative to bus architecture.
An NoC is made of connects to router to router, router to hardmacro.
This paper presents a hardmacro placement method which optimizes network topology so that communication energy is minimized.
Two hardmacros which frequently communicate with each other are placed closely so that it takes fewer communication hops.
Our hardmacro placement method places a pair of hardmacros which frequently communicate with each other closely so that the hardmacros communicate with low energy.
Our experimental results show that reduced 65% of communication hops from worst placement result.
Keyword (in Japanese) (See Japanese page) 
(in English) Network-on-Chip / NoC / communication energy / placement / optimization / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-147, pp. 123-128, March 2009.
Paper # VLD2008-147 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-147

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC 
Sub Title (in English)  
Keyword(1) Network-on-Chip  
Keyword(2) NoC  
Keyword(3) communication energy  
Keyword(4) placement  
Keyword(5) optimization  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroshi Uchikoshi  
1st Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
2nd Author's Name Makoto Sugihara  
2nd Author's Affiliation Toyohashi University of Technology/JST-CREST (Toyohashi Univ. of Tech./JST-CREST)
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Speaker Author-1 
Date Time 2009-03-12 13:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-147 
Volume (vol) vol.108 
Number (no) no.478 
Page pp.123-128 
#Pages 6 
Date of Issue 2009-03-04 (VLD) 

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