IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-03-12 15:40
A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking
Keita Saito, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-151
Abstract (in Japanese) (See Japanese page) 
(in English) To meet increasing demands of link speeds and complex network applications, network processor is required because it has higher speed than general-purpose processor and more flexibility than ASIC. Task Chaining is widely used technique that alllows a network application to be partitioned into multiple modules and be assigned to processor cores for pipeline processing; however, it requires mapping multiple tasks onto different processing elements. Not to lose its high speed and programmability, task mapping cannot take long time and must get great performance out of network processor. In this paper, we present a backtracking-based search approach to solve this problem. In order to conduct task mapping in a short time and improvement of the accuracy of the solution as well, we introduce the existing heauristics that were used for decreasing the communication cost and load-balancing, and then limit the range of the search around the solution obtained by those techniques. The experimental results showed that the proposal method could find the solution with higher throughput when compared with existing technique.
Keyword (in Japanese) (See Japanese page) 
(in English) Network Processor / Task Chaining / Task Mapping / Multithreading / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-151, pp. 147-152, March 2009.
Paper # VLD2008-151 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-151

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking 
Sub Title (in English)  
Keyword(1) Network Processor  
Keyword(2) Task Chaining  
Keyword(3) Task Mapping  
Keyword(4) Multithreading  
1st Author's Name Keita Saito  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Nozomu Togawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Tatsuo Ohtsuki  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2009-03-12 15:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-151 
Volume (vol) vol.108 
Number (no) no.478 
Page pp.147-152 
Date of Issue 2009-03-04 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan