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Paper Abstract and Keywords
Presentation 2009-03-12 17:05
Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC
Hiroki Kuniyasu, Tomoyuki Kishida, Tian Song, Takashi Shimamoto (Tokushima Univ.) VLD2008-154
Abstract (in Japanese) (See Japanese page) 
(in English) H.264/AVC introduced a certain numbers of novel prediction modes compared to the previous standards. Rate-Distortion Optimization(RDO) which is a method used for selecting optimal prediction mode from the candidate prediction modes, induces drastic computation complexity increasing. In particular, the transform and quantization of the H.264/AVC, namely DQ Engine in this work, with the calculation of generated bits introduced, needs many processing cycles due to frequently using for the RDO process. Therefore, there is high requirement for fast architecture of DQ engine and CAVLC in the case of real-time encoding for high definition applications. In this work, an efficient architecture for fast DQ module is proposed. Proposed architecture introduced an early detection architecture for all-zero block which can cut down the redundant process. A bit estimation architecture is also introduced into the DQ Engine to fulfill fast estimation of the generated bits. Proposed architecture are described with Verilog-HDL and implemented on FPGA(Xilinx Vertex-5) device. Proposed architecture can be implemented with only 34,352 gates. The simulation results show that the proposed method can achieve fast processing of DQ with almost no image quality loss. From the results, our architecture is possible to achieve real-time encoding for full HD resolution when operating at about 100MHz clock.
Keyword (in Japanese) (See Japanese page) 
(in English) RDO / DCT / CAVLC / VLSI / Architecture / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 478, VLD2008-154, pp. 165-170, March 2009.
Paper # VLD2008-154 
Date of Issue 2009-03-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-154

Conference Information
Committee VLD  
Conference Date 2009-03-11 - 2009-03-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for a System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2009-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC 
Sub Title (in English)  
Keyword(1) RDO  
Keyword(2) DCT  
Keyword(3) CAVLC  
Keyword(4) VLSI  
Keyword(5) Architecture  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroki Kuniyasu  
1st Author's Affiliation Tokushima University (Tokushima Univ.)
2nd Author's Name Tomoyuki Kishida  
2nd Author's Affiliation Tokushima University (Tokushima Univ.)
3rd Author's Name Tian Song  
3rd Author's Affiliation Tokushima University (Tokushima Univ.)
4th Author's Name Takashi Shimamoto  
4th Author's Affiliation Tokushima University (Tokushima Univ.)
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Speaker Author-1 
Date Time 2009-03-12 17:05:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-154 
Volume (vol) vol.108 
Number (no) no.478 
Page pp.165-170 
#Pages 6 
Date of Issue 2009-03-04 (VLD) 

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