Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-05-14 13:30
Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3
Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) RECONF2009-2
Abstract (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor Array(DRPA) has been received an attention as a flexible and power efficient off-loading engine for embedded devices. MuCCRA, our original DRPA, has been developed to research on the methond for lowering its power consumption. In this paper, the third prototype chip MuCCRA-3 is introduced. As a result of evaluation, MuCCRA-3 has 30 times better energy efficiency than MuCCRA-1, implemented with 180nm process, and 200 times than the DSP with 130nm process.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor Array / Real Chip / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 26, RECONF2009-2, pp. 7-12, May 2009.
Paper # RECONF2009-2 
Date of Issue 2009-05-07 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2009-2

Conference Information
Committee RECONF  
Conference Date 2009-05-14 - 2009-05-15 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2009-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processor Array  
Keyword(2) Real Chip  
Keyword(3)  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yoshihiro Yasuda  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Yoshiki Saito  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Toru Sano  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Masaru Kato  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Hideharu Amano  
5th Author's Affiliation Keio University (Keio Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2009-05-14 13:30:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2009-2 
Volume (vol) vol.109 
Number (no) no.26 
Page pp.7-12 
#Pages 6 
Date of Issue 2009-05-07 (RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan