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Paper Abstract and Keywords
Presentation 2009-06-12 10:20
In-situ etching by CBr4 in InP heterojunction bipolar transistors with buried SiO2 wire
Naoaki Takebe, Hiroaki Yamashita, Shinnosuke Takahashi, Hisashi Saito, Takashi Kobayashi, Yasuyuki Miyamoto, Kazuhito Furuya (Tokyo Inst. of Tech.) ED2009-46
Abstract (in Japanese) (See Japanese page) 
(in English) In order to obtain high-speed InP heterojunction bipolar transistors (HBTs), it is necessary to reduce the base-collector capacitance ($C_{\{BC}}$) under the base electrode. Thus we proposed buried glass heterojunction bipolar transistor (BG-HBT) which had SiO_2 wires in the collector. By SiO_2 wires buried in the InP collector layer, we can obtain reduced $C_{\{BC}}$ because of its low dielectric constant. From equivalent circuit analysis, reduction of InP thickness over buried SiO_2 ($T_{\{top}}$) enhance the performance of BG-HBT. To realize such structure, we introduced in-situ etching of InP layer by introduction of CBr_4 after SiO_2 buried growth. Ttop was reduced to 1/4 by in-situ etching with the flat InP surface. We confirmed that C-doping by etching has no effect on fabrication of a BG-HBT by SIMS analysis.
Keyword (in Japanese) (See Japanese page) 
(in English) heterojunction bipolar transistor / InP / MOVPE / SiO2 wire / CBr4 / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 81, ED2009-46, pp. 51-55, June 2009.
Paper # ED2009-46 
Date of Issue 2009-06-04 (ED) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ED  
Conference Date 2009-06-11 - 2009-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ED 
Conference Code 2009-06-ED 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) In-situ etching by CBr4 in InP heterojunction bipolar transistors with buried SiO2 wire 
Sub Title (in English)  
Keyword(1) heterojunction bipolar transistor  
Keyword(2) InP  
Keyword(3) MOVPE  
Keyword(4) SiO2 wire  
Keyword(5) CBr4  
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Keyword(7)  
Keyword(8)  
1st Author's Name Naoaki Takebe  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Hiroaki Yamashita  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Shinnosuke Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
4th Author's Name Hisashi Saito  
4th Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
5th Author's Name Takashi Kobayashi  
5th Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
6th Author's Name Yasuyuki Miyamoto  
6th Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
7th Author's Name Kazuhito Furuya  
7th Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker Author-1 
Date Time 2009-06-12 10:20:00 
Presentation Time 25 minutes 
Registration for ED 
Paper # ED2009-46 
Volume (vol) vol.109 
Number (no) no.81 
Page pp.51-55 
#Pages 5 
Date of Issue 2009-06-04 (ED) 

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