講演抄録/キーワード |
講演名 |
2009-06-24 15:15
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits ○Fumitaka Iga・Masashi Kamiyanagi・Shoji Ikeda(Tohoku Univ.)・Katsuya Miura(Tohoku Univ./Hitachi)・Jun Hayakawa(Hitachi)・Haruhiro Hasegawa・Takahiro Hanyu・Hideo Ohno・Tetsuo Endoh(Tohoku Univ.) ED2009-53 SDM2009-48 エレソ技報アーカイブへのリンク:ED2009-53 SDM2009-48 |
抄録 |
(和) |
In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal / 1-poly Gate 0.14${\rm \mu}$m CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line.This MTJ of 60x180${\rm nm^2}$ achieves a large change in resistance of 3.52k${\rm \Omega}$ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320${\rm \mu}$A that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device. |
(英) |
In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal / 1-poly Gate 0.14${\rm \mu}$m CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line.This MTJ of 60x180${\rm nm^2}$ achieves a large change in resistance of 3.52k${\rm \Omega}$ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320${\rm \mu}$A that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device. |
キーワード |
(和) |
磁気トンネル接合 (MTJ) / スピン注入磁化反転RAM (STT-RAM) / メモリインロジック / MgOバリア / スピントロニクス / トンネル磁気抵抗効果 (TMR) / 磁気抵抗メモリ (MRAM) / スピン注入磁化反転 |
(英) |
magnetic tunnel junction (MTJ) / spin-transfer torque RAM (STT-RAM) / memory-in-logic / MgO barrier / spintronics / tunnel magnetoresistance (TMR) / magnetoresistive RAM (MRAM) / current induced magnetization switching |
文献情報 |
信学技報, vol. 109, no. 98, SDM2009-48, pp. 13-16, 2009年6月. |
資料番号 |
SDM2009-48 |
発行日 |
2009-06-17 (ED, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
ED2009-53 SDM2009-48 エレソ技報アーカイブへのリンク:ED2009-53 SDM2009-48 |