Paper Abstract and Keywords |
Presentation |
2009-07-16 11:25
Low Energy Building Design in Packet Buffer Architecture with Deterministic Performance Guarantee Kazuya Zaitsu (Osaka City Univ.), Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas Technology), Koji Yamamoto (Renesas Design), Kazunari Inoue (Renesas Technology), Shingo Ata, Ikuo Oka (Osaka City Univ.) SDM2009-100 ICD2009-16 Link to ES Tech. Rep. Archives: SDM2009-100 ICD2009-16 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
To design guaranteed high-performance router, it is problem that packet buffer is non-deterministic. We propose Head Buffer MMU which can realize high-speed data transfer guaranteed packet buffer. Moreover, the MMU can provide large buffers with cost-effective and low power consumption. In this paper, we design the bank selection circuit which can guarantee DRAM high-speed data transfer in Head Buffer MMU. We then show power saving of DRAM by using the bank selection circuit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Packet buffer / Rate guarantee / Circuit design / MMU / Head Buffer / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 134, ICD2009-16, pp. 17-22, July 2009. |
Paper # |
ICD2009-16 |
Date of Issue |
2009-07-09 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2009-100 ICD2009-16 Link to ES Tech. Rep. Archives: SDM2009-100 ICD2009-16 |
|