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Paper Abstract and Keywords
Presentation 2009-09-18 13:10
High-density Implementation for Reconfigurable Device MPLD
Hiroaki Toguchi, Masanori Asaeda, Yutaro Oda, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN CO.LTD) RECONF2009-35
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, a lot of Programmable Logic Device (PLD) such as Field Programmable Gate Array (FPGA) has been used. As a new PLD, MPLD which have features of memory and logic circuit has been proposed.
MPLD consists of MLUTs. MLUT has functions as LUT, switch block, and memory. By placing and connecting the neighboring arrays of MLUTs, MPLD can behave like conventional FPGA. Invesdigation on constitution method for MPLD architecture was considers,
and performed tip trial manufacture for prototype MPLD(ProtMPLD)．However, ProtMPLD is designed on the by the basic constitution of MPLD, but it did not perform enough for a practical circuit.
In this paper，long interconnects as like as Torus Network line was introduced in the MPLD and evaluated by implimenting carry look ahead adder．As a result, the long interconnects as like as Torus Network decreases the number of MLUT used as wiring function.
And enables High-density aplication on implementation for reconfigurable device MPLD
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / MPLD / memory / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 198, RECONF2009-35, pp. 97-102, Sept. 2009.
Paper # RECONF2009-35 
Date of Issue 2009-09-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2009-35

Conference Information
Committee RECONF  
Conference Date 2009-09-17 - 2009-09-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Utsunomiya Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Sysytems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2009-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High-density Implementation for Reconfigurable Device MPLD 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) MPLD  
Keyword(3) memory  
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1st Author's Name Hiroaki Toguchi  
1st Author's Affiliation Hiroshima City University Graduated School (Hiroshima City Univ.)
2nd Author's Name Masanori Asaeda  
2nd Author's Affiliation Hiroshima City University Graduated School (Hiroshima City Univ.)
3rd Author's Name Yutaro Oda  
3rd Author's Affiliation Hiroshima City University Graduated School (Hiroshima City Univ.)
4th Author's Name Naoki Hirakawa  
4th Author's Affiliation Hiroshima City University Graduated School (Hiroshima City Univ.)
5th Author's Name Kazuya Tanigawa  
5th Author's Affiliation Hiroshima City University Graduated School (Hiroshima City Univ.)
6th Author's Name Tetsuo Hironaka  
6th Author's Affiliation Hiroshima City University Graduated School (Hiroshima City Univ.)
7th Author's Name Masayuki Sato  
7th Author's Affiliation TAIYO YUDEN CO.LTD (TAIYO YUDEN CO.LTD)
8th Author's Name Takashi Ishiguro  
8th Author's Affiliation TAIYO YUDEN CO.LTD (TAIYO YUDEN CO.LTD)
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Speaker Author-1 
Date Time 2009-09-18 13:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2009-35 
Volume (vol) vol.109 
Number (no) no.198 
Page pp.97-102 
#Pages 6 
Date of Issue 2009-09-10 (RECONF) 

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