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Paper Abstract and Keywords
Presentation 2009-09-24 13:50
Fast Circuit Simulation Based on GPGPU-LIM and Its Estimation
Yuta Inoue, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2009-30 NLP2009-66
Abstract (in Japanese) (See Japanese page) 
(in English) With the progress of high-density integration technology of the circuits, a variety of signal and power integrity problems have become serious and important for the electronic design. This paper describes the fast circuit simulation by GPGPU-LIM (GPGPU-based Latency Insertion Method). First, LIM is reviewed, which is a fast algorithm. Next, implementation of LIM on the general purpose computing on graphic processing unit (GPGPU) is shown. Furthermore, this method is applied to the simulation of power distribution networks (PDNs). Finally, it is confirmed that GPGPU-based LIM is very practical and efficient for the large-scale PDN simulations.
Keyword (in Japanese) (See Japanese page) 
(in English) GPGPU / Latency Insertion Method / Transient Analysis / Parallel Computing / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 199, CAS2009-30, pp. 37-42, Sept. 2009.
Paper # CAS2009-30 
Date of Issue 2009-09-17 (CAS, NLP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CAS NLP  
Conference Date 2009-09-24 - 2009-09-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiroshima Univ. Higashi Senda Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CAS 
Conference Code 2009-09-CAS-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fast Circuit Simulation Based on GPGPU-LIM and Its Estimation 
Sub Title (in English)  
Keyword(1) GPGPU  
Keyword(2) Latency Insertion Method  
Keyword(3) Transient Analysis  
Keyword(4) Parallel Computing  
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1st Author's Name Yuta Inoue  
1st Author's Affiliation Shizuoka University (Shizuoka Univ.)
2nd Author's Name Tadatoshi Sekine  
2nd Author's Affiliation Shizuoka University (Shizuoka Univ.)
3rd Author's Name Hideki Asai  
3rd Author's Affiliation Shizuoka University (Shizuoka Univ.)
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Speaker Author-1 
Date Time 2009-09-24 13:50:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2009-30, NLP2009-66 
Volume (vol) vol.109 
Number (no) no.199(CAS), no.200(NLP) 
Page pp.37-42 
#Pages
Date of Issue 2009-09-17 (CAS, NLP) 


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