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| Presentation | 2009-09-25 11:05 High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard Akiyuki Nagashima, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)  VLD2009-38 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Low Density Parity Check (LDPC) code is expected to be an error orrecting code for next generation networks since it shows high error correcting performance and is incorporated into IEEE802.11n, the next standard of wireless network. In this paper, we propose a multi-rate compatible irregular LDPC decoder enhancing column operation parallelism. Focusing on column-wise parallelism of column operations, our LDPC decoder increases usage rate of operational units and throughput by calculating all inputs simultaneously. The decoder achieves $28\%$ increase in throughput compared to resent architectures. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | LDPC decoder / Irregular / Multi-Rate / column operation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 201, VLD2009-38, pp. 51-56, Sept. 2009. | |
| Paper # | VLD2009-38 | |
| Date of Issue | 2009-09-17 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-38 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2009-09-24 - 2009-09-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Osaka University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Physical design, etc |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2009-09-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard |
| Sub Title (in English) | |
| Keyword(1) | LDPC decoder |
| Keyword(2) | Irregular |
| Keyword(3) | Multi-Rate |
| Keyword(4) | column operation |
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| 1st Author's Name | Akiyuki Nagashima |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Nozomu Togawa |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Masao Yanagisawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Tatsuo Ohtsuki |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-09-25 11:05:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2009-38 |
| Volume (vol) | vol.109 |
| Number (no) | no.201 |
| Page | pp.51-56 |
| #Pages | 6 |
| Date of Issue | 2009-09-17 (VLD) |
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