| Paper Abstract and Keywords |
| Presentation |
2009-09-29 13:10
An Multi-rate LDPC decoder system on FPGA Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Satoshi Goto (Waseda Univ.) IT2009-32 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper presents a novel early termination (ET) scheme for layered Low-density Parity-check (LDPC) code decoding. The proposed scheme has better BER performance compared to the early works. It improves BER performance by at least 0.2 dB. A case study using an 802.16e LDPC code and our proposed ET scheme on FPGA is also presented in this paper. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
LDPC / Early Termination / FPGA / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 109, no. 212, IT2009-32, pp. 1-4, Sept. 2009. |
| Paper # |
IT2009-32 |
| Date of Issue |
2009-09-22 (IT) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
IT2009-32 |
| Conference Information |
| Committee |
IT |
| Conference Date |
2009-09-29 - 2009-09-30 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Sophia Univ. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
LDPC codes, general |
| Paper Information |
| Registration To |
IT |
| Conference Code |
2009-09-IT |
| Language |
English |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
An Multi-rate LDPC decoder system on FPGA |
| Sub Title (in English) |
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| Keyword(1) |
LDPC |
| Keyword(2) |
Early Termination |
| Keyword(3) |
FPGA |
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| 1st Author's Name |
Xiongxin Zhao |
| 1st Author's Affiliation |
Graduate school of IPS, Waseda University (Waseda Univ.) |
| 2nd Author's Name |
Zhixiang Chen |
| 2nd Author's Affiliation |
Graduate school of IPS, Waseda University (Waseda Univ.) |
| 3rd Author's Name |
Xiao Peng |
| 3rd Author's Affiliation |
Graduate school of IPS, Waseda University (Waseda Univ.) |
| 4th Author's Name |
Satoshi Goto |
| 4th Author's Affiliation |
Graduate school of IPS, Waseda University (Waseda Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2009-09-29 13:10:00 |
| Presentation Time |
25 minutes |
| Registration for |
IT |
| Paper # |
IT2009-32 |
| Volume (vol) |
vol.109 |
| Number (no) |
no.212 |
| Page |
pp.1-4 |
| #Pages |
4 |
| Date of Issue |
2009-09-22 (IT) |