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| Presentation | 2009-12-02 10:20 A Circuit Design Method based on Foreknown Regularity between I/O Jin Sato, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.)  CPM2009-134 ICD2009-63 Link to ES Tech. Rep. Archives: CPM2009-134 ICD2009-63 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The paper proposes a method of designing an arithmetic unit based on the regularity of the output depending on input patterns. The advantages of this method are reduced number of gates without sacrificing high speed calculation and easy modularization scheme for high precision arithmetic unit. The soundness of this method is confirmed by the implementation on FPGA. This circuit design method based on foreknown regularity between input and output pattern can be applied not only to arithmetic operation such as addition/subtraction, but also to other circuit units. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Modularization / Foreknown Regularity / Circuit Design MethodTemplate / Circuit Area Reduction / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 318, ICD2009-63, pp. 1-6, Dec. 2009. | |
| Paper # | ICD2009-63 | |
| Date of Issue | 2009-11-25 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2009-134 ICD2009-63 Link to ES Tech. Rep. Archives: CPM2009-134 ICD2009-63 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Circuit Design Method based on Foreknown Regularity between I/O |
| Sub Title (in English) | |
| Keyword(1) | Modularization |
| Keyword(2) | Foreknown Regularity |
| Keyword(3) | Circuit Design MethodTemplate |
| Keyword(4) | Circuit Area Reduction |
| Keyword(5) | |
| Keyword(6) | |
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| 1st Author's Name | Jin Sato |
| 1st Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 2nd Author's Name | Tsugio Nakamura |
| 2nd Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 3rd Author's Name | Hiroshi Kasahara |
| 3rd Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
| 4th Author's Name | Narito Fuyutsume |
| 4th Author's Affiliation | Tokyo Denki University (Tokyo Denki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-12-02 10:20:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | CPM2009-134, ICD2009-63 |
| Volume (vol) | vol.109 |
| Number (no) | no.317(CPM), no.318(ICD) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2009-11-25 (CPM, ICD) |
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