Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-12-03 13:25
Detection of Fault Candidate portions by DEF data Visualization
Kazuaki Kishi, Masaru Sanada (Kochi Univ. of Tech.) VLD2009-53 DC2009-40
Abstract (in Japanese) (See Japanese page) 
(in English) Line information visualized using DEF data, and layout data of unique fault formations makes it possible to indicate fault formations and to detect the intended line names. The former formations are applied to discern the physical analysis positions for real fault LSI. The latter names are used to pull out the gate circuit positions connect to net names among cell circuit. The above data combined with connection information of transistor level has been led to an easy fault diagnosis technology based on voltage value.
Keyword (in Japanese) (See Japanese page) 
(in English) LSI / DEF / fault diagnosis / fault candidate / visualization / nat name / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 316, DC2009-40, pp. 85-88, Dec. 2009.
Paper # DC2009-40 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-53 DC2009-40

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To DC 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Detection of Fault Candidate portions by DEF data Visualization 
Sub Title (in English)  
Keyword(1) LSI  
Keyword(2) DEF  
Keyword(3) fault diagnosis  
Keyword(4) fault candidate  
Keyword(5) visualization  
Keyword(6) nat name  
Keyword(7)  
Keyword(8)  
1st Author's Name Kazuaki Kishi  
1st Author's Affiliation Kochi University of Technology (Kochi Univ. of Tech.)
2nd Author's Name Masaru Sanada  
2nd Author's Affiliation Kochi University of Technology (Kochi Univ. of Tech.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2009-12-03 13:25:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # VLD2009-53, DC2009-40 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.85-88 
#Pages 4 
Date of Issue 2009-11-25 (VLD, DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan