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Paper Abstract and Keywords
Presentation 2009-12-03 14:05
Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity
Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) VLD2009-55 DC2009-42
Abstract (in Japanese) (See Japanese page) 
(in English) Increase of power dissipation and IR-drop during scan-shifting operation and/or capture operation is still challenging problem for LSI testing. It is known that power dissipation during scan-shifting can be reduced with DFT techniques. As for capture power reduction, post-ATPG test modification is the preferable solution since it does not cause circuit modification, test data inflation and ATPG modification consists of X-identification and X-filling. Although the existing X-identification identifies a plenty number of X-bits, some test cubes have a relatively small number of X-bits. Usually a desirable number of X-bits for each test cube must be different depending on X-filling and its purposes. In this paper we propose a new X-identification to control the X-bit distribution according to a given required distribution. Experimental results demonstrate the proposed method to optimize the percentage of X-bits to reduce switching activity.
Keyword (in Japanese) (See Japanese page) 
(in English) ATPG / X-bit / X-identification / X-filling / post-ATPG test modification / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 316, DC2009-42, pp. 95-100, Dec. 2009.
Paper # DC2009-42 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-55 DC2009-42

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To DC 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity 
Sub Title (in English)  
Keyword(1) ATPG  
Keyword(2) X-bit  
Keyword(3) X-identification  
Keyword(4) X-filling  
Keyword(5) post-ATPG test modification  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Isao Beppu  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Institute of Tech)
2nd Author's Name Kohei Miyase  
2nd Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech/JST)
3rd Author's Name Yuta Yamato  
3rd Author's Affiliation Kyushu Institute of Technology (Kyushu Institute of Tech)
4th Author's Name Xiaoqing Wen  
4th Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech/JST)
5th Author's Name Seiji Kajihara  
5th Author's Affiliation Kyushu Institute of Technology/JST CREST (Kyushu Institute of Tech/JST)
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Speaker Author-1 
Date Time 2009-12-03 14:05:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # VLD2009-55, DC2009-42 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.95-100 
#Pages 6 
Date of Issue 2009-11-25 (VLD, DC) 

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