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| Presentation | 2009-12-04 10:00 A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.)  VLD2009-58 DC2009-45 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, a method which detects timing error points by using the logic simulation with back annotation of delay time variation by crosstalk is proposed. As an experiment, this method was applied to evaluate a multiplier and a CPU, and the result was that the rate of crosstalk points in the circuit was less than 40 %, and the rate of crosstalk points which generate timing errors was less than 10 %. This method reduces the correction points of wire by comparison to the conventional method, and will be able to accelerate the frequency of high performance circuits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Crosstalk / Logic Simulation / Circuit Design / EDA / CAD / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 315, VLD2009-58, pp. 119-124, Dec. 2009. | |
| Paper # | VLD2009-58 | |
| Date of Issue | 2009-11-25 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-58 DC2009-45 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk |
| Sub Title (in English) | |
| Keyword(1) | Crosstalk |
| Keyword(2) | Logic Simulation |
| Keyword(3) | Circuit Design |
| Keyword(4) | EDA |
| Keyword(5) | CAD |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masayuki Kobayashi |
| 1st Author's Affiliation | Kochi University (Kochi Univ.) |
| 2nd Author's Name | Wataru Sento |
| 2nd Author's Affiliation | Kochi University (Kochi Univ.) |
| 3rd Author's Name | Masahiko Toyonaga |
| 3rd Author's Affiliation | Kochi University (Kochi Univ.) |
| 4th Author's Name | Michiaki Muraoka |
| 4th Author's Affiliation | Kochi University (Kochi Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-12-04 10:00:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | VLD2009-58, DC2009-45 |
| Volume (vol) | vol.109 |
| Number (no) | no.315(VLD), no.316(DC) |
| Page | pp.119-124 |
| #Pages | 6 |
| Date of Issue | 2009-11-25 (VLD, DC) |
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