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| Presentation | 2009-12-04 10:20 A Study of two input LUT array type programmable logic architecture for cryptographic processing Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.)  RECONF2009-49 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Various kinds of block ciphers must be supported in order to communicate safely in computer networks by using the consumer electric appliances or the mobile devices. The high-speed encryption cannot be realized by the software implementation on low-performance CPU. The dedicated encryption hardware in the ASIC represents high performance, however, the handling of newly-developed cipher algorithm is difficult. In this study, we examined the novel programmable logic architecture which supports various kinds of cipher algorism by changing configuration data. This programmable logic architecture composed of two components; one is the ePLXcrypt which calculate bit-wise operation, the other is the MEMcrypt which calculate S-Box operation. The ePLXcrypt is modified for cipher processing from the conventional ePLX architecture in order to reduce macro area. The MEMcrypt, which calculate SBox procedure in DES and AES cipher, is designed by verilog HDL, and verified by Modelsim. The area estimation of MEMcrypt is also carried out by SRAM cell layout using 0.18 um CMOS process. We investigated the MEMcrypt area by comparing the chip area estimation derived from logic synthesis. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | programmable device / LUT matrix / encryption circuit / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 320, RECONF2009-49, pp. 49-54, Dec. 2009. | |
| Paper # | RECONF2009-49 | |
| Date of Issue | 2009-11-26 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2009-49 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of two input LUT array type programmable logic architecture for cryptographic processing |
| Sub Title (in English) | |
| Keyword(1) | programmable device |
| Keyword(2) | LUT matrix |
| Keyword(3) | encryption circuit |
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| 1st Author's Name | Ai Nakanishi |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Kouta Ishibashi |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Yuuichirou Kurokawa |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Takeshi Fujino |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-12-04 10:20:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | RECONF2009-49 |
| Volume (vol) | vol.109 |
| Number (no) | no.320 |
| Page | pp.49-54 |
| #Pages | 6 |
| Date of Issue | 2009-11-26 (RECONF) |
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