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Paper Abstract and Keywords
Presentation 2009-12-04 15:00
Evaluation of Energy Consumption on Multipliers Using the Sum of Operands
Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) VLD2009-66 DC2009-53
Abstract (in Japanese) (See Japanese page) 
(in English) We evaluate dynamic energy consumption of multipliers using the sum of operands we have proposed before.
The multipliers using sum of operands reduce the number of partial product bits efficiently, and are designed in the smaller number of circuit elements than existing multipliers.
The dynamic energy consumption can be reduced by reducing the number of signal transitions.
Reducing the number of circuit elements is one of the method of reducing the signal transitions.
On the other hand, our previous work shows that energy consumption on the parallel multipliers depends on not only the number of circuit elements but also circuit construction.
We evaluate energy consumption of the multipliers composed of the smaller number of circuit elements, and show how reducing the circuit elements effects reducing the dynamic energy consumption.
Simulation results show that the energy consumption of the Wallace multipliers is less than the multipliers using the sum of operands.
It is shown that reducing the number of circuit elements does not necessarily lead to reducing the dynamic energy consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) paralle multiplier / energy consumption / the number of circuit elements / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 315, VLD2009-66, pp. 173-178, Dec. 2009.
Paper # VLD2009-66 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-66 DC2009-53

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Energy Consumption on Multipliers Using the Sum of Operands 
Sub Title (in English)  
Keyword(1) paralle multiplier  
Keyword(2) energy consumption  
Keyword(3) the number of circuit elements  
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1st Author's Name Hirotaka Kawashima  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Naofumi Takagi  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker Author-1 
Date Time 2009-12-04 15:00:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2009-66, DC2009-53 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.173-178 
#Pages 6 
Date of Issue 2009-11-25 (VLD, DC) 

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