講演抄録/キーワード |
講演名 |
2009-12-11 13:25
Note on Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test Anis Uzzaman(Cadence Design Systems/Tokyo Metro. Univ)・Brion Keller・Tom Snethen(Cadence)・Kazuhiko Iwasaki・○Masayuki Arai(Tokyo Metro. Univ) DC2009-57 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation (OPCG) for use during ATPG and how that can also help with low power delay test. The system described in this paper automatically generates mode initialization sequence, setup sequence, test sequence and others and enables low power aware delay test when faster on product clocks are present on board. This system has successfully been used to process delay test for ASIC chips even with 22 PLLs on board. |
キーワード |
(和) |
/ / / / / / / |
(英) |
OPCG / delay test / low power / eda / asic / ate / / |
文献情報 |
信学技報, vol. 109, no. 334, DC2009-57, pp. 7-12, 2009年12月. |
資料番号 |
DC2009-57 |
発行日 |
2009-12-04 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
DC2009-57 |