| Paper Abstract and Keywords |
| Presentation |
2010-01-21 15:00
Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP Tomohiro Kaizu (JAIST), Yoshinao Isobe (AIST), Masato Suzuki (JAIST) CST2009-40 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, you can synthesize concurrent systems from multiple sequence diagrams. We define a new CSP operator for the synthesis of sequence diagrams. We also developed a tool to achieve this technique, and confirmed effectiveness of this approach. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Sequence Diagram / Process Algebra / CSP / Process Synthesis / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 109, Jan. 2010. |
| Paper # |
|
| Date of Issue |
2010-01-14 (CST) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
CST2009-40 |
| Conference Information |
| Committee |
MSS |
| Conference Date |
2010-01-21 - 2010-01-22 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Toyota Central R&D Labs. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Embedded System, etc |
| Paper Information |
| Registration To |
MSS |
| Conference Code |
2010-01-CST |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP |
| Sub Title (in English) |
|
| Keyword(1) |
Sequence Diagram |
| Keyword(2) |
Process Algebra |
| Keyword(3) |
CSP |
| Keyword(4) |
Process Synthesis |
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| 1st Author's Name |
Tomohiro Kaizu |
| 1st Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
| 2nd Author's Name |
Yoshinao Isobe |
| 2nd Author's Affiliation |
National Institute of Advanced Industrial Science and Technology (AIST) |
| 3rd Author's Name |
Masato Suzuki |
| 3rd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
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| Speaker |
Author-1 |
| Date Time |
2010-01-21 15:00:00 |
| Presentation Time |
25 minutes |
| Registration for |
MSS |
| Paper # |
CST2009-40 |
| Volume (vol) |
vol.109 |
| Number (no) |
no.367 |
| Page |
pp.19-24 |
| #Pages |
6 |
| Date of Issue |
2010-01-14 (CST) |