Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-01-27 09:00
Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) VLD2009-84 CPSY2009-66 RECONF2009-69
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival in the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) Recon gurable VLSI / Multiple voltage control / Dynamic voltage and frequency scaling / Asynchronous architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-69, pp. 95-99, Jan. 2010.
Paper # RECONF2009-69 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-84 CPSY2009-66 RECONF2009-69

Conference Information
Committee IPSJ-SLDM VLD CPSY RECONF  
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control 
Sub Title (in English)  
Keyword(1) Recon gurable VLSI  
Keyword(2) Multiple voltage control  
Keyword(3) Dynamic voltage and frequency scaling  
Keyword(4) Asynchronous architecture  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shota Ishihara  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Zhengfan Xia  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Masanori Hariyama  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Michitaka Kameyama  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2010-01-27 09:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2009-84, CPSY2009-66, RECONF2009-69 
Volume (vol) vol.109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.95-99 
#Pages 5 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]

(Line Height for English Pages: 1)
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan